eda与vhdl课后答案(2)
END count;
ARCHITECTURE a OF count IS
BEGIN
PROCESS(clk)
IF clk'EVENT AND clk='1' THEN
q<=q+1;
END PROCESS;
END a;
10、修改正确如下所示：
SIGNAL invalue:IN INTEGER RANGE 0 TO 15;
SIGNAL outvalue:OUT STD_LOGIC;
CASE invalue IS
WHEN 0=>outvalue<='1';
WHEN 1=>outvalue<='0';
WHEN OTHERS=>NULL;
END CASE;
11、修改正确如下所示：
BEGIN
SIGNAL a,b,c:STD_LOGIC;
pro1:PROCESS(clk)
BEGIN
IF NOT (clk'EVENT AND clk='1') THEN
x<=a XOR b OR c;
END IF;
END PROCESS;
END;
12、(1) PROCESS(…) --本题中两条IF语句均为信号c进行可能赋值，VHDL语言不允许 IF a=b THEN
c<=d;
END IF;
IF a=4 THEN
c<=d+1;
END IF;
END PROCESS;
(2)ARCHITECTURE behave OF mux IS --同时为q进行多次可能赋值，VHDL语言不允许 BEGIN
q<=i0 WHEN a='0' AND b='0' ELSE '0'; --WHEN ELSE语句语法错误
q<=i1 WHEN a='0' AND b='1' ELSE '0';
q<=i2 WHEN a='1' AND b='0' ELSE '0';
q<=i3 WHEN a='1' AND b='1' ELSE '0';
END behave;
13、next1<=1101 WHEN (a='0' AND b='0') ELSE
d WHEN a='0' ELSE
c WHEN b='1' ELSE
1011;
15、(1)、STD_LOGIC_UNSIGNED
(2)、GENERIC
(3)、IN
(4)、width-1(7)
(5)、counter_n
(6)、“00000000”
(7)、clk’EVENT AND clk=’1’
(8)、ELSIF
(9)、END IF
(10)、q<= count
16、修改正确如下所示：
LIBRARY IEEE;
ENTITY CNT10 IS
PORT ( clk: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CNT10;
ARCHITECTURE bhv OF CNT10 IS
SIGNAL q1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) begin –begin修改为THEN
IF q1 < 9 THEN --q1为STD_LOGIC数据类型，而9为整型不可直接比较
q1 <= q1 + 1; -- q1为STD_LOGIC数据类型，而1为整型不可直接相加
ELSE
q1 <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
q <= q1;
END bhv;
17、使用IF语句实现
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21 IS
PORT(ain,bin,sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
cout:OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END;
ARCHITECTURE bhv OF mux21 IS
SIGNAL cout_tmp:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
PROCESS(ain,bin,sel)
BEGIN
IF (sel="00") THEN cout_tmp<=ain OR bin;
ELSIF (sel="01") THEN cout_tmp<=ain XOR bin;
ELSIF (sel="10") THEN cout_tmp<=ain AND bin;
ELSE cout_tmp<=ain NOR bin;
END IF;
END PROCESS;
cout<=cout_tmp;
END bhv;